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Title:
VARIABLE GAIN AMPLIFIER CIRCUIT USING VARIABLE IMPEDANCE CIRCUIT
Document Type and Number:
Japanese Patent JP2004336129
Kind Code:
A
Abstract:

To provide a variable gain amplifier circuit in which a layout area is reduced, a noise characteristic is not deteriorated and an input signal is gain-controlled and amplified in accordance with a digital control signal of n-bits in terms of geometrical series.

The circuit is provided with an operation amplifier 4, a first variable impedance connected to an input terminal 1 and the operation amplifier 4 of the circuit, a second variable impedance connected to an inverse input terminal and an output terminal of the operation amplifier, a third variable impedance whose one end is connected to the inverse input terminal of the operation amplifier, a fourth variable impedance whose one end is connected to the input terminal of the circuit and whose other end is connected to the other end of the third variable impedance, and a fifth variable impedance whose one end is connected to the other end of the third variable impedance and whose other end is connected to an output terminal 3 of the operation amplifier 4. The first to third variable impedances are controlled by a high-order bit group, and the fourth and fifth variable impedances are controlled by a low-order bit group.


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Inventors:
SHIRAI YOSHIHIRO
Application Number:
JP2003125369A
Publication Date:
November 25, 2004
Filing Date:
April 30, 2003
Export Citation:
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Assignee:
CANON KK
International Classes:
H03G3/02; H03G1/00; H03G3/10; (IPC1-7): H03G3/02; H03G3/10
Attorney, Agent or Firm:
Jyohei Yamashita
Hiroshi Shimura