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Title:
VARIABLE LENGTH CODE DEMODULATOR
Document Type and Number:
Japanese Patent JPH03145223
Kind Code:
A
Abstract:

PURPOSE: To reduce the circuit scale without deteriorating the performance by selectively outputting a fixed length code from 1st and 2nd conversion tables depending on a bit length code.

CONSTITUTION: A 1st conversion table 2 converts a variable length code into a conversion code with a short bit length when the variable length code is made up of a bit length longer than the bit length of a high-order bit and outputs the result to a 2nd conversion table 3. The 2nd conversion table 3 receives the conversion code as a high-order bit of an address and a low-order bit of the variable length code as a low-order bit of the address and converts the preceding variable length code into a fixed length code and outputs the converted code to a selector 4. The selector 4 based on the bit length code representing the bit length pattern outputs selectively the fixed length code from the 1st and 2nd conversion tables 2 and 3. Thus, the circuit scale is reduced without deteriorating the conversion performance.


Inventors:
KONISHI KAZUO
Application Number:
JP28346889A
Publication Date:
June 20, 1991
Filing Date:
October 30, 1989
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
H03M7/42; (IPC1-7): H03M7/40
Attorney, Agent or Firm:
Susumu Ito



 
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