Title:
VARIABLE SPEED DATA TRANSMITTER AND VARIABLE SPEED DATA RECEIVER
Document Type and Number:
Japanese Patent JP3192901
Kind Code:
B2
Abstract:
PURPOSE: To prevent transmission efficiency from being reduced by easily conducting error recovery with a simple configuration in the transmission of VBR information.
CONSTITUTION: An information generating period signal CR is generated by using a 1/M frequency divider 13 to apply 1/M frequency division to a source clock of an encoder 10. VBR data amt. generated from the encoder 10 are counted by a counter 12 and stored in a buffer 11 and an adaptor section 14 reads the VBR data stored in the buffer 11 for each CR by a count value of the counter 12. The adaptor section 14 processes the read VBR data into a packet. The adaptor section 14 prepares the packet by providing dummy data DD generated by a provision section 16 so that the length of the packet is an integer multiple of a data length processed by an adaptor section 17 and a length DL of the dummy data to the VBR data based on the result of CRC of the VBR data by an arithmetic section 15. The adaptor section 17 divides the packet received from the adaptor section 14 into plural segments with a fixed length. An ATM cell header is provided to each segment by an ATM-S18.
Inventors:
Masaki Yamauchi
Tsuneo Hamada
Masanori Nozaki
Tsuneo Hamada
Masanori Nozaki
Application Number:
JP398495A
Publication Date:
July 30, 2001
Filing Date:
January 13, 1995
Export Citation:
Assignee:
Oki Electric Industry Co., Ltd.
International Classes:
H04Q3/00; H04L12/28; H04L47/43; H04L47/431; (IPC1-7): H04L12/28; H04L12/56
Domestic Patent References:
| JP5336154A |
Other References:
「Ｂ−ＩＳＤＮ絵とき読本」オーム社、Ｐ１０７−１１４
Attorney, Agent or Firm:
Nobuyuki Kudo