Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
ばらつき分布シミュレーション装置及び方法
Document Type and Number:
Japanese Patent JP5139391
Kind Code:
B2
Abstract:
A circuit simulation apparatus according to an embodiment of the present invention calculates a set value of a SPICE parameter of a MOSFET to carry out a variation analysis on a semiconductor circuit including the MOSFET. The apparatus includes a storage part configured to store an intermediate model expression that includes a variable related to a manufacture condition or device structure of the MOSFET as a variable affecting variation characteristics of the MOSFET, the intermediate model expression being formed with a universal function having a physical correlation between a physical amount defined by the variable and the SPICE parameter, a setting part configured to set information about the variable included in the intermediate model expression, a calculation part configured to calculate the set value of the SPICE parameter by using the information set in the setting part and the intermediate model expression stored in the storage part, and an output part configured to output process variation dependency of the semiconductor circuit.

Inventors:
Fujii Megumi
Yoshitomi Sadayuki
Naoki Wakida
Itano Yuka
Application Number:
JP2009221388A
Publication Date:
February 06, 2013
Filing Date:
September 25, 2009
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
Toshiba Corporation
International Classes:
G06F17/50; H01L21/82
Domestic Patent References:
JP6215059A
JP2002318829A
JP7282097A
JP6052254A
Other References:
久本大 他,シリコン半導体デバイスの展望,日立評論,2007年 4月,第89巻,第4号,p.14-21
Peter A. Stolk et al.,Modeling Statistical DopantFluctuations in MOS Transistors,IEEE TRANSACTIONS ON ELECTRON DEVICES,1998年 9月,VOL.45,NO.9,p.1960-1971
Attorney, Agent or Firm:
Kenji Yoshitake
Yasukazu Sato
Hiroshi Yoshimoto
Yasushi Kawasaki
Jie Yamanoi



 
Previous Patent: JPS5139390

Next Patent: DIAGNOSING DEVICE FOR AVIONICS APPARATUS