Title:
VECTOR LOAD PROCESSING METHOD
Document Type and Number:
Japanese Patent JPS63285668
Kind Code:
A
Abstract:
PURPOSE:To shorten a period during which a vector register is occupied in order to hold the loaded vector data and to decrease the number of desired vector registers, by correcting a reference instruction so that the coincidence is secured between a vector register set at a loading destination and a reference vector register for the reference instruction. CONSTITUTION:A vector load instruction is detected and a reference instruction corresponding to said load instruction is retrieved. Then the vector load instruction is moved to a position close as much as possible to the reference instruction as long as the optimization is possible. Then more reference instructions are retrieved out of the subsequent intermediate code strings and a vector load instruction equivalent to the first vector load instruction is produced and put into a place near the reference instruction when a reference instruction is retrieved and can be optimized. This processing is continued for the intermediate code strings set within a prescribed range. Thus it is possible to secure the effect of optimization for decrease of the number of desired vector registers even when plural reference instructions are scattered in response to a single vector load instruction.
Inventors:
SERIZAWA HIDEO
AOKI MASAKI
AOKI MASAKI
Application Number:
JP12151787A
Publication Date:
November 22, 1988
Filing Date:
May 19, 1987
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
G06F9/45; G06F15/78; G06F17/16; (IPC1-7): G06F9/44; G06F15/347
Attorney, Agent or Firm:
Sadaichi Igita