Title:
ベクトル処理装置、及び、追い越し制御回路
Document Type and Number:
Japanese Patent JP3988144
Kind Code:
B2
Abstract:
A vector processing apparatus includes a main memory (200), an instruction issuing section (2), an overtaking control circuit (1) and an instruction executing section (3). The instruction issuing section sequentially issues instructions. A first instruction of the instructions is issued, and then a second instruction thereof is issued, a fourth instruction thereof is issued before a third instruction thereof which is issued after the second instruction. The overtaking control circuit outputs the instructions received from the instruction issuing section to the instruction executing section in an order determined based on whether each of the first and second instructions as two of the received instructions belongs to a first specific instruction group, whether each of the first and second instructions belongs to a second specific instruction group in the first specific instruction group, whether the fourth instruction as one of the received instructions is a fourth specific instruction group, whether a third instruction as one of the received instructions belongs to a third specific instruction group, and whether an address area of the main memory relating to the third instruction and an address area of the main memory relating to each of the first and second instructions do not overlap at all. The instruction executing section executes the instructions received from the overtaking control circuit in an order of reception and to access the main memory in response to each of first to third instructions of the instructions.
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Inventors:
Yasumasa Saita
Application Number:
JP2004047066A
Publication Date:
October 10, 2007
Filing Date:
February 23, 2004
Export Citation:
Assignee:
NEC
International Classes:
G06F9/38; G06F17/16; G06F9/00; G06F12/00; G06F12/02; G06F15/00
Domestic Patent References:
| JP10269199A | ||||
| JP2253470A | ||||
| JP2002297566A | ||||
| JP2001195389A |
Attorney, Agent or Firm:
Minoru Kudo