Title:
VECTOR PROCESSOR
Document Type and Number:
Japanese Patent JPS59163671
Kind Code:
A
Abstract:
PURPOSE:To execute consecutive vector instruction in overlapping by performing reading and writing independently of each other for a vector buffer and at the same time providing a means which identifies each state in response to the vector buffer. CONSTITUTION:Vector buffers 4-19 can be read and written independently of or simultaneously with each other, and a means is provided to each of these buffers to detect the write timing of the head element corresponding to each buffer. Thus it is possible to detect the timing where all buffers serving as the operands of a certain instruction are not set under a write waiting mode and at the same time the buffer to which the result is written is not under a writing mode. Then the reading is started in said timing for the buffers 4-19 serving as the operands. Thus it is frequently possible to process the corresponding instruction and its preceding instruction in overlapping with each other. As a result, the processing speed can be increased for a vector processor.
Inventors:
YANO HARUO
Application Number:
JP3942683A
Publication Date:
September 14, 1984
Filing Date:
March 09, 1983
Export Citation:
Assignee:
NIPPON ELECTRIC CO
International Classes:
G06F17/16; G06F15/78; (IPC1-7): G06F15/347
Domestic Patent References:
| JPS5688559A | 1981-07-18 | |||
| JPS5688561A | 1981-07-18 | |||
| JPS5725069A | 1982-02-09 |
Attorney, Agent or Firm:
Kusano Takashi