Title:
VERTICAL DEFLECTION CIRCUIT
Document Type and Number:
Japanese Patent JP3902071
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a vertical deflection circuit capable of suppressing a dynamic range and achieving the reduction of power consumption in a deflection circuit.
SOLUTION: A vertical pulse signal VS is formed from a video signal by a synchronizing separator circuit 101. A vertical sawtooth waveform is adjusted according to a vertical sawtooth gain set value GD and is outputted, and a vertical retrace line reference pulse VP1 is outputted by a vertical sawtooth generator circuit 102. A retrace line pulse KP is outputted based on the reference pulse VP1 and retrace line width setting data KHD by a counter circuit 103 and a retrace line pulse generation circuit 104, and the retrace line pulse KP is superposed on a vertical sawtooth waveform VN1 by a retrace line circuit 105. An output signal VN2 is converted to a digital signal DS by an output circuit 106. The high frequency component of the signal DS is removed by an LPF circuit 107. A vertical sawtooth waveform having no discrete part can be outputted, power consumption can be reduced, and an excessive dynamic range can be prevented.
Inventors:
Nobuo Takeya
Ryuichi Shibuya
Hiroshi Moribe
Ryuichi Shibuya
Hiroshi Moribe
Application Number:
JP2002160843A
Publication Date:
April 04, 2007
Filing Date:
May 31, 2002
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
H04N3/16; G09G1/04; (IPC1-7): H04N3/16; G09G1/04
Domestic Patent References:
| JP200194816A |
Attorney, Agent or Firm:
Yoshito Fukushima