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Patent Searching and Data


Title:
VERTICAL DEFLECTION OUTPUT CIRCUT
Document Type and Number:
Japanese Patent JPS5483311
Kind Code:
A
Abstract:

PURPOSE: To decrease the loss of electric power by means of a simple circuit constitution by controlling output transistors respectively at the first half and the latter half of the vertical blanking interval.

CONSTITUTION: When a collector current of output transistor TR 6 flows in diode 9, forward voltage is generated on the both terminals of diode 9 and the portion between the base and emitter of TR 10, a switching element, is biased reversely by forward voltage VBE; TR 10 is cut off at the latter half of the vertical blanking interval and the first half of the vertical scanning interval. At the first half of the vertical blanking interval and the latter half of the vertical scanning interval, the base current of TR 10 flows from power source 2 and capacity 4 is charged by the emitter current of TR 10; the charged voltage rises from voltage E1 to E2. As the result, a turnover current enough to supply to deflection coil 8 is obtained during the vertical blanking interval.


Inventors:
SHIRAKI TAKESHI
KUBOTA SADAO
Application Number:
JP15054277A
Publication Date:
July 03, 1979
Filing Date:
December 16, 1977
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H04N3/16; (IPC1-7): H04N3/16