Title:
VERTICAL MOS SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
Document Type and Number:
Japanese Patent JP2003303960
Kind Code:
A
Abstract:
To solve the problem wherein the on-resistance is large in the switching of an MOS transistor and power consumption becomes high, since parasitic junction FET resistance is high in the conventional vertical MOS transistor.
In the MOS transistor 31, a gate electrode 48 is formed by a second trench 46. Then, a drain lead-out region is formed by a first trench 39 and a buried layer 38. Therefore, there are no parasitic junction FETs in an epitaxial layer 33 set to be the drain region of a lower region in a P- type diffusion region 44. As a result, parasitic resistance can be reduced, when the MOS transistor 31 is turned on, and the power consumption can be reduced.
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Inventors:
OTAKE SEIJI
KOUCHI SATOSHI
KOUCHI SATOSHI
Application Number:
JP2002106318A
Publication Date:
October 24, 2003
Filing Date:
April 09, 2002
Export Citation:
Assignee:
SANYO ELECTRIC CO
International Classes:
H01L29/78; (IPC1-7): H01L29/78
Attorney, Agent or Firm:
Masano Shibano