Title:
FORMING METHOD OF ELEMENT ISOLATING REGION
Document Type and Number:
Japanese Patent JP3124441
Kind Code:
B2
Abstract:
PURPOSE: To lessen a bird's beak in length keeping a transistor adequate in threshold value when an element isolating region of a transistor is formed.
CONSTITUTION: A first underlay oxide film 102, a polysilicon film 103, and a first silicon nitride film 104 are successively formed on a silicon substrate 101, and furthermore the first silicon nitride film 104, the polysilicon film 103, the first underlay oxide film 102, and a part of the silicon substrate 101 to serve as an element isolating region are etched using a photoresist as a mask so deep (below 1/3 as thick as an element isolating oxide film) as to make the length of a bird's beak and the threshold value of a field effect transistor adequate. A second underlay oxide film 107 and a second silicon nitride film 108 are formed, and then a nitride film side wall 109 above 25nm in thickness is formed. An element isolating oxide film 110 is formed through selective oxidation using a nitride film as a mask. By this setup, an element isolating region below 0.2μm in length can be formed in a DRAM cell pattern.
Inventors:
Noritomo Shimizu
Yasushi Naito
Yuichi Hirofuji
Yasushi Naito
Yuichi Hirofuji
Application Number:
JP15611294A
Publication Date:
January 15, 2001
Filing Date:
July 07, 1994
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
H01L21/316; H01L21/76; H01L21/8242; H01L27/08; H01L27/10; H01L27/108; (IPC1-7): H01L27/08; H01L21/316; H01L21/76; H01L21/8242; H01L27/108
Domestic Patent References:
| JP4268747A | ||||
| JP63217640A |
Attorney, Agent or Firm:
Hiroshi Maeda (2 outside)
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