VERTICAL TRANSISTOR AND ITS MANUFACTURING METHOD

Japanese Patent JP3870323

B2

PROBLEM TO BE SOLVED: To provide a vertical transistor that can be manufactured without employing an ultramodern high-accuracy lithographic technology, has less defects, and can be integrated with higher density, and to provide a method of manufacturing the transistor.
SOLUTION: This vertical transistor includes a vertical channel comprising a source region 150 formed in the surface layer section of a semiconductor substrate 100, a drain region 310 formed above the region 150, and a first silicon layer 200 which is in contact with the source region 150 on one side and with the drain region 310 on the other. This transistor also includes a gate electrode 450 which is formed to surround the side faces of the vertical channel and drain region 310 and electrically insulated from the source region 150 by a nitride film pattern 115 formed on the upper surface of the substrate 100, from the drain region 310 by a nitride film spacer 320 formed on the side face of the region 310, and from the vertical channel by a gate oxide film 400 formed to cover the side face of the channel and an exposed region below the drain region 310.

Yu Jingdong

JP2002378127A

January 17, 2007

December 26, 2002

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HYNIX SEMICONDUCTOR INC.

H01L29/78; H01L21/336; (IPC1-7): H01L29/78

JP5183158A
JP11214684A
JP2000091578A

Eiji Saegusa
Kakehi Yuro
Takeshi Ohara
Hiroji Nakagawa
Yasumitsu Tate
Kenji Saito
Jun Fujii
Hitoshi Seki
Mutsuko Nakano
Shinichi Mashita
Ryuji Inuchi

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