Title:
映像フレームコーデックアーキテクチャ
Document Type and Number:
Japanese Patent JP7057378
Kind Code:
B2
Abstract:
Techniques and apparatuses are described for video frame codec architectures. A frame decompressor decompresses compressed frames to produce decompressed frames. A frame decompressor controller arbitrates shared access to the frame decompressor. Multiple cores of an SoC request to receive a decompressed frame from the frame decompressor via the frame decompressor controller. The frame decompressor controller can implement a request queue and can order the servicing of requests based on priority of the requests or requesting cores. The frame decompressor controller can also establish a time-sharing protocol for access by the multiple cores. In some implementations, a video decoder is logically integrated with the frame decompressor and stores portions of a decompressed frame in a video buffer, and a display controller retrieves the portions for display using a synchronization mechanism. In analogous manners, a frame compressor controller can arbitrate shared access to a frame compressor for the multiple cores.
Inventors:
Kousela, Aki Oscari
Lautio, Bille-Micco
Lautio, Bille-Micco
Application Number:
JP2019559770A
Publication Date:
April 19, 2022
Filing Date:
July 13, 2018
Export Citation:
Assignee:
Google LLC
International Classes:
H04N19/42; H04N19/426; H04N19/44
Domestic Patent References:
| JP2009302704A | ||||
| JP2007266970A |
Attorney, Agent or Firm:
Fukami patent office