To provide a video processing device which can provide a faster deinterlace speed and a superior screen quality, using hardware.
A video processing device is provided with a video decoder 104, a deinterlace module 106, a PIP module 108, and a PIP characteristics control device 110. The video decoder 104 receives a video signal 112 to be decoded and generates a digital video signal 114. The deinterlace module 106 receives the digital video signal 114 and generates a non-interlace signal 116. The PIP module 108 overlays the non-interlace signal 116 and a screen signal 120, based on a PIP characteristic control signal 118 and generates a parent-child screen 122 to be reproduced by a display device 124. A PIP characteristics control device 110 outputs the PIP characteristics control signal 118, based on a PIP command 128.
CHANG WEN-CHIEN
YO ZUISHO
Masahiro Ishino