Title:
VIDEO SCRAMBLE AND DESCRAMBLE SYSTEM
Document Type and Number:
Japanese Patent JPS6262686
Kind Code:
A
Abstract:
PURPOSE:To integrate a descramble part and a digital video processing circuit into one body and to reduce cost and a circuit scale by inserting the information for determining a reference address required for the descramble with a fixed amplitude and the same frequency and phase as a burst signal during a horizontal synchronizing signal period. CONSTITUTION:A video signal has a picture pattern part switched in a time base direction at the xth address of an original signal. In order top prevent both end signals of the xth address and the (x-1)th address from being distorted due to a band control or the like, they are removed during a descramble time. Accordingly, in order to carry out the descramble, the picture pattern parts are successively rearranged so as to dispose from 0 address to xMAX address. Herein, a digital synchronizing signal DS multiplexed to a horizontal synchronizing signal has its frequency the same as a burst signal BU and has a phase succeeding to the phase of the burst signal of the same line. Accordingly, a chrominance signal demodulating pulse can be formed from the digital synchronizing signal.
Inventors:
NAKAGAWA MASAKI
KUDO YUKINORI
KUDO YUKINORI
Application Number:
JP20266885A
Publication Date:
March 19, 1987
Filing Date:
September 13, 1985
Export Citation:
Assignee:
TOSHIBA CORP
International Classes:
H04K1/04; G06F21/10; H04N7/167; H04N7/169; (IPC1-7): H04K1/04; H04N7/167
Attorney, Agent or Firm:
Takehiko Suzue
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