Title:
VIDEO SIGNAL CONVERTING DEVICE AND DISPLAY DEVICE EQUIPPED WITH THE SAME
Document Type and Number:
Japanese Patent JP3637516
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To make it possible to use the whole screen for display even when a video signal of lower resolution than any supported display mode is inputted by providing a memory control circuit, etc., which shifts the operation start period of a line memory for the writing operation from that of a line memory for the read operation by adjusting the operation start period based upon a horizontal synchronizing signal according to an interval data signal.
SOLUTION: A memory operation control circuit 610 of a memory control circuit 600 receives data signals HD and TA from a microcomputer 100 and a write pixel clock signal W-Dc1k and a read pixel clock signal R-Dc1k from a clock generating circuit 200 and generates a memory write enable signal and a memory read enable signal for selecting a line memory which performs the writing operation and a line memory which performs the reading operation. This constitution can makes a display over the entire screen of a display device even when a video signal is supplied in a display mode of lower resolution than any display mode that the display device supports.
Inventors:
Gold
Application Number:
JP18095497A
Publication Date:
April 13, 2005
Filing Date:
July 07, 1997
Export Citation:
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
H04N11/04; G06T3/40; G09G3/36; G11B20/00; H04N5/66; H04N7/01; H04N9/30; H04N9/64; G09G3/20; G09G5/18; (IPC1-7): H04N9/64; H04N7/01; H04N9/30
Domestic Patent References:
| JP7245732A | ||||
| JP5150219A | ||||
| JP5292477A |
Attorney, Agent or Firm:
Miaki Kametani
Tetsuo Kanamoto
Tetsuo Kanamoto