PURPOSE: To reduce the number of circuit components, the chip size and the cost by providing a master latch circuit for fetching a signal data signal, and a data signal latch circuit for each channel.

CONSTITUTION: A master latch circuit 2 for fetching a signal data signal is provided and a data signal latch circuit 7 comprising a data signal distribution switch 8 operated by clock signals 1-n corresponding to a data signal connecting in parallel for each channel, and a capacitor C is provided at the post-stage are provided. Then a clock signal is supplied to the data signal latch circuits 7 of each channel corresponding to each channel of a serial data signal, they are operated to distribute and latch the serial data signal for each channel, and it is outputted to control the serial data signal as a data signal for each channel. Thus, the number of circuit components is reduced, the chip size is decreased and the cost is reduced.