Title:
VITERBI DECODER
Document Type and Number:
Japanese Patent JP3277451
Kind Code:
B2
Abstract:
PURPOSE: To obtain the Viterbi decoder in which accuracy of error correction is enhanced.
CONSTITUTION: An equalizer 1 applies waveform equalization to an input signal to convert the signal into a signal with a partial response characteristic. A level controller 2 eliminates level fluctuation of an output signal of the equalizer 1. A converter 3 digitizes an output signal of the level controller 2. A PR equalizer 41 applies waveform equalization to most significant bit data of an output signal of the converter 3 to convert the signal into a signal having a partial response characteristic. A delay device 42 matches a phase of the output signal of the converter 3 with a phase of an output signal of the PR equalizer 41. An adder 43 takes a difference between an output signal of the PR equalizer 41 and an output signal of the delay device 42. A filter 44 extracts a low frequency component of the output signal of the adder 43. Delay devices 45, 46 match a phase of the output signal of the converter 3 with a phase of an output signal of the filter 44. An adder 47 takes a difference between the output signal of the filter 44 and an output signal of the delay device 46. A Viterbi decoding circuit decodes an output signal of the adder 47.
Inventors:
Shigenobu Masahiro
Kensuke Fujimoto
Kensuke Fujimoto
Application Number:
JP34194495A
Publication Date:
April 22, 2002
Filing Date:
December 27, 1995
Export Citation:
Assignee:
ソニー株式会社
International Classes:
G11B20/18; H03H21/00; H03M13/23; H03M13/41; H04B3/06; H04L25/08; (IPC1-7): H03M13/41; G11B20/18; H03H21/00; H04B3/06; H04L25/08
Domestic Patent References:
| JP7296524A | ||||
| JP8265176A | ||||
| JP8321143A |
Attorney, Agent or Firm:
Akira Koike (2 outside)