Title:
VITERBI DECODING CIRCUIT
Document Type and Number:
Japanese Patent JP3258174
Kind Code:
B2
Abstract:
PURPOSE: To attain high speed operation by feeding back a difference from bus metrics of each of survived buses for succeeding arithmetic operation so as to prevent an increase in the arithmetic operation without degrading the accuracy of the arithmetic operation thereby reducing number of stages of arithmetic operation in the feedback loop.
CONSTITUTION: Data obtained by quantizing a reproduced signal from an optical disk and equalized by the PR system are applied to a difference branch metric(BM) arithmetic means 1 for each clock, in which the difference from the BMs in all branches is calculated and the result is outputted. A survived bus discrimination means 2 calculates an output of the means 1 and a difference between the BMs between survived buses of one preceding clock of a latch means 5 to discriminate the survived bus. A difference BM arithmetic means 3 uses the difference from the BMs of the survived bus from the means 1, 5 to calculate the BM of the bus transited from each survived bus. An output of the means 3 is selected depending on an output of the means 2 by a difference BM selection means 4. The means 5 latches the output of the means 4 as a difference from the BMs between the survived buses. A data decoding means 6 is used to decode the data by using the output of the means 2.
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Inventors:
Tsuneo Fujiwara
Application Number:
JP17260294A
Publication Date:
February 18, 2002
Filing Date:
July 25, 1994
Export Citation:
Assignee:
Sharp Corporation
International Classes:
G06F11/10; G11B20/18; H03M13/23; H03M13/41; (IPC1-7): H03M13/41; G06F11/10; G11B20/18
Domestic Patent References:
| JP6252779A |
Attorney, Agent or Firm:
Yoshio Kawaguchi (1 person outside)