PURPOSE: To attain the oscillation at an optional frequency by providing a 1st delay circuit retarding a signal and a 2nd delay circuit connecting in parallel with the 1st delay circuit, selecting one of the 1st and 2nd delay circuits and using the selected circuit.
CONSTITUTION: Other terminal of a capacitor 4 connects to ground, an output terminal of a Schmitt trigger inverter 5 connects to an input terminal of a clocked inverter 6 and one terminal of a delay element 7, and the other terminal of the delay element 7 connects to an input terminal of a clocked inverter 8. The charge stored in the capacitor 4 is discharged and when an input voltage of the Schmitt trigger inverter 5 drops and reaches a threshold level or below, the output signal is inverted to a high level and an output signal of the clocked inverter 6 goes to a low level. The operation is repeated and the oscillator is oscillated. The oscillating frequency depends on a signal propagation delay time of the inverter 2, the Schmitt trigger inverter 5 and the clocked inverter 6 and the time constant of an integration circuit comprising a transistor(TR) 3 and a capacitor 4.
JPS6165620A | 1986-04-04 | |||
JPS60250712A | 1985-12-11 | |||
JPS63185108A | 1988-07-30 |