Title:
VOLTAGE CONVERSION CIRCUIT FOR SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP3652793
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To minimize transient DC voltage generated at transition of an input signal, and to suppress power consumption and to attain a high speed response by preparing an auxiliary control device to be driven in accordance with an input signal to control the control terminal of an active load.
SOLUTION: When an input signal IN is an 'H' level, an NMOS transistor(TR) 10 is turned to a conductive state and an NMOS TR 20 is turned to a non-conductive state due to inversion by an inverter 25. A PMOS TR 70 receiving the input signal IN by its gage is turned to a non-conductive state and a PMOS TR 60 receiving the inverted input signal, the inverse of IN, by its gate is turned to a conductive state. Thereby a node N5 is sufficiently charged by a VPP in an auxiliary control device 100 in addition to the charge of a control node N2 by a PMOS TR 15. Since the influence of a coupling effect of gate voltage is also suppressed, the TR 5 is extremely quickly turned to a non-conductive state, a node N1 is quickly discharged, the logic of the node N2 is quickly defined, and the output OUT of a booster Vpp is extracted. Also when the signal IN is in an 'L' level, similar operation is executed.
Inventors:
Golden bell
Application Number:
JP17114696A
Publication Date:
May 25, 2005
Filing Date:
July 01, 1996
Export Citation:
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
G11C5/14; G11C11/407; H01L27/092; H03K19/0185; H01L21/8238; H03K19/0948; (IPC1-7): H03K19/0185; H01L21/8238; H01L27/092; H03K19/0948
Domestic Patent References:
| JP2188024A | ||||
| JP2145018A | ||||
| JP7193488A |
Attorney, Agent or Firm:
Yasunori Otsuka
Shiro Takayanagi
Yasuhiro Otsuka
Shuji Kimura
Shiro Takayanagi
Yasuhiro Otsuka
Shuji Kimura