Title:
VOLTAGE FLUCTUATION COMPENSATING METHOD OF PLL CIRCUIT AND ITS PLL CIRCUIT
Document Type and Number:
Japanese Patent JP3963282
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To operate in different feeding voltages with one PLL by detecting the value of power supply voltage to a PLL circuit and adjusting an operation frequency of the PLL circuit based on a detection value.
SOLUTION: A detector detects the value of power supply voltage. An output 13 of the detector is connected to a PLL 14. The detector of power supply voltage operates by comparing the power supply voltage with reference voltage that is not affected by the power supply voltage. The PLL 14 includes a frequency divider 26 between Vco/ICO 24 and a phase detector 18. When it is detected that the power supply voltage is 5V as is shown by a control line 13, a multiplexer 28 selects an output 27 from the divider 26. In such cases, the frequency range of the PLL is adjusted based on the detected value of the power supply voltage by changing the reference voltage or reference current. This makes it possible to obtain a PLL which has an operation frequency characteristic that does not depend on power supply voltage.
Inventors:
Daolong Chen
Application Number:
JP24401095A
Publication Date:
August 22, 2007
Filing Date:
September 22, 1995
Export Citation:
Assignee:
MAGNACHIP SEMICONDUCTOR LTD
International Classes:
H03L1/00; H03K3/354; H03L7/08; H03L7/099; H03L7/18; H03L7/183; (IPC1-7): H03L7/08; H03L7/18
Domestic Patent References:
| JP5327425A | ||||
| JP4165716A |
Foreign References:
| US5331295 | ||||
| US5175512 |
Attorney, Agent or Firm:
Yoshiaki Nishiyama