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Patent Searching and Data


Title:
VOLTAGE LOWERING DETECTION CIRCUIT FOR BACKUP BATTERY
Document Type and Number:
Japanese Patent JPH0261932
Kind Code:
A
Abstract:

PURPOSE: To conduct a stable voltage abnormality display even if battery voltage is repeatedly varied due to the variation of load by providing the level difference between abnormality and recovery discriminant levels respectively when the battery boltage lowers and rises.

CONSTITUTION: When battery partial pressure voltage V1 is higher than reference voltage VR1, the output voltage of comparators CMP1 and CMP2 becomes L, and the voltage of both A and B terminals becomes L with both photocouplers PC1 and PC2 driven. On the other hand, when the voltage V1 is lower than the voltage VR1 and higher than reference voltage VR2, the output voltage of CP1 is H and that of CP2 is L, and the voltage of the A terminal and the B terminal becomes H and L respectively. Moreover, when V1 is lower than VR2, the output voltage of CP1 and CP2 is H, and that of both A and B terminals becomes H. The output voltage of the C terminal of an A.C. voltage detection means 4 becomes H or L by ON or OFF of A.C. voltage. The output of these A-C terminals is processed in a logic circuit 5, and when V1 becomes lower than VR2, voltage abnormality is displayed with an abnormality display means 6.


Inventors:
FUJIKI HITOSHI
Application Number:
JP21268888A
Publication Date:
March 01, 1990
Filing Date:
August 26, 1988
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC WORKS LTD
International Classes:
G01R31/36; G01R19/165; G08B21/00; G08B21/08; H01J7/00; H02J9/00; (IPC1-7): G01R19/165; G01R31/36; G08B21/00; H01J7/00
Domestic Patent References:
JPS60243579A1985-12-03
JPS5450931A1979-04-21
Attorney, Agent or Firm:
Hiroyuki Nakai