PURPOSE: To allow the circuit to cope with multi-station broadcast such as CATV by storing a tuning voltage data in an EEPROM and a data ROM separately so as to use the number of sufficient storable channels.
CONSTITUTION: A CPU 2 designates an address to an EEPROM 5 and a data ROM 22 corresponding to input channel numbers (CH1, CH2,...CHn) and reads a channel data of the designated address, respectively. Both data are inputted to an adder circuit 23, where they are added and the data is restored to a required bit number of the original tuning voltage data, and inputted to a D/A converter 6 via an arithmetic RAM 4. When the tuning voltage data has 14-bit, the high-order 7-bit is stored in the data ROM 22, the low-order 7-bit is stored in the EEPROM 5 while separately, assigning, then the capacity of the EEPROM 5 is halved to that of a conventional circuit.
JPS5787624A | 1982-06-01 | |||
JPS5457901A | 1979-05-10 |