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Title:
ウエハレベルパッケージおよびキャパシタ
Document Type and Number:
Japanese Patent JP6769480
Kind Code:
B2
Abstract:
A wafer level package which includes an IC chip; a rewiring layer on the IC chip; and a capacitor embedded in the rewiring layer.

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Inventors:
Tatsuya Funaki
Tokuyuki Inoue
Application Number:
JP2018516950A
Publication Date:
October 14, 2020
Filing Date:
April 27, 2017
Export Citation:
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Assignee:
MURATA MANUFACTURING CO.,LTD.
International Classes:
H01L23/12; H01G4/30; H01G4/33
Domestic Patent References:
JP2008227266A
JP2004172526A
JP2013131459A
Foreign References:
WO2015118901A1
Attorney, Agent or Firm:
Norihito Yamao
Yoshida Tamaki



 
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