Title:
WATCHDOG TIMER CIRCUIT
Document Type and Number:
Japanese Patent JPS6355601
Kind Code:
A
Abstract:
PURPOSE:To stop and restart execution of a control circuit during the working of a watchdog time circuit by inhibiting the output of a reset signal as long as the control circuit does not deliver a state signal to read a program to be executed. CONSTITUTION:A watchdog timer circuit consists of an output port 2 connected to a CPU1 via a data bus DB, a 1st multivibrator M1 which works with input of an up-edge, and a 2nd multivibrator M2 which works with input of a down- edge. Then a fetch terminal of the CPU1 is connected to a clear terminal of the multivibrator M2 via a circuit a diode D, a resistance R, a capacitor C and a buffer gate G. In such a constitution, this timer circuit decides discontinuation of its execution from the interruption of a fetch signal and delivers no reset signal that is used to reset the CPU1 when this CPU1 stops execution of its program. Thus the execution of the timer circuit is continued from the state set before its discontinuation according to the action of a program counter in the restart of execution.
Inventors:
KOMODA YOSHIYUKI
SUZUKI YOSHIHARU
SUZUKI YOSHIHARU
Application Number:
JP20063586A
Publication Date:
March 10, 1988
Filing Date:
August 26, 1986
Export Citation:
Assignee:
MATSUSHITA ELECTRIC WORKS LTD
International Classes:
G05B9/02; G05B23/02; (IPC1-7): G05B9/02; G05B23/02
Attorney, Agent or Firm:
Ishida Choshichi
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