Title:
ウェルレジスタ及びポリシリコンレジスタ
Document Type and Number:
Japanese Patent JP6600318
Kind Code:
B2
Abstract:
An integrated circuit containing a well resistor has STI field oxide and resistor dummy active areas in the well resistor. STI trenches are etched and filled with trench fill dielectric material. The trench fill dielectric material is removed from over the active areas by a CMP process, leaving STI field oxide in the STI trenches. Subsequently, dopants are implanted into a substrate in the well resistor area to form the well resistor. An integrated circuit containing a polysilicon resistor has STI field oxide and resistor dummy active areas in an area for the polysilicon resistor. A layer of polysilicon is formed and planarized by a CMP process. A polysilicon etch mask is formed over the CMP-planarized polysilicon layer to define the polysilicon resistor. A polysilicon etch process removes polysilicon in areas exposed by the polysilicon etch mask, leaving the polysilicon resistor.
Inventors:
Stefan Keith Heinrich Varna
Douglas pea barret
Alwin Jay Csao
Douglas pea barret
Alwin Jay Csao
Application Number:
JP2016569994A
Publication Date:
October 30, 2019
Filing Date:
May 27, 2015
Export Citation:
Assignee:
Texas Instruments Japan Ltd.
Texas Instruments Incorporated
Texas Instruments Incorporated
International Classes:
H01L21/822; H01L21/321; H01L21/76; H01L21/768; H01L27/04
Domestic Patent References:
| JP2006269573A |
Foreign References:
| US7141831 | ||||
| US20130203226 | ||||
| US7403094 |
Attorney, Agent or Firm:
Kyozo Katayose