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Title:
WIRE BONDER
Document Type and Number:
Japanese Patent JPH0373547
Kind Code:
A
Abstract:

PURPOSE: To improve efficiency by a method wherein pattern recognition is performed as to a special pattern part at one constant point on a chip part after position correction and before bonding so that if the pattern matches with a stored recognition pattern for position confirmation, bonding is done and if it does not match, processing proceeds to a subsequent wiring substrate.

CONSTITUTION: A bonding control mechanism 17 controls a stage 3 and moves to a position of a position correction mark 7 previously stored for a chip part 1, and requests output of position correction data from a control circuit 14. The control circuit 14 records a position correction recognition range 9 with a television camera 11, and an image processing circuit 12 creates a binary image. The image is compared with a binary image stored in a position correction reference pattern memory 15 for the chip part 1 to output a difference from a reference pattern, i.e., position correction data, which has been factorized in the horizontal direction (X), the vertical direction (Y) and the rotary direction (θ), and the bonding control mechanism 17 corrects the position of the chip part 1 based on the output data. Thus, it is possible to prevent defective parts from flowing to subsequent process due to erroneous mounting, and therefore efficient wire bonding can be performed.


Inventors:
ISHIBASHI TAKAO
Application Number:
JP21031189A
Publication Date:
March 28, 1991
Filing Date:
August 14, 1989
Export Citation:
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Assignee:
NEC CORP
International Classes:
H01L21/60; (IPC1-7): H01L21/60
Attorney, Agent or Firm:
Uchihara Shin



 
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