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Title:
WIRE LOOP FORM, SEMICONDUCTOR DEVICE HAVING THE SAME, WIRE BONDING METHOD, AND SEMICONDUCTOR MANUFACTURING APPARATUS
Document Type and Number:
Japanese Patent JP2004172477
Kind Code:
A
Abstract:

To provide a stable and low wire loop form and the wire loop form having little damage at a neck height part, a wire bonding method, a semiconductor manufacturing apparatus for applying the method and a semiconductor device having the wire loop form.

In the wire loop form for connecting between a first bonding point and a second bonding point with a wire, the pinnacle of the ball at the first bonding point including a part of the wire is made to be squashed. The forming method for connecting between the first bonding point and the second bonding point with the bonding wire comprises a first process for connecting the wire to the first bonding point, a second process for controlling the wire loop by moving a capillary upward, horizontally, etc., a third process for bonding the wire to the vicinity of the pinnacle of the bonded ball at the first bonding point A, and a fourth process for sending out the wire toward the second bonding point and connecting the wire to the second bonding point Z while controlling the wire loop by moving the capillary upward, horizontally, etc.


Inventors:
FUJISAWA HIROO
Application Number:
JP2002338296A
Publication Date:
June 17, 2004
Filing Date:
November 21, 2002
Export Citation:
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Assignee:
KAIJO KK
International Classes:
H01L21/60; B23K20/00; B23K20/10; H01L21/607; (IPC1-7): H01L21/60
Attorney, Agent or Firm:
Koichi Fujii
Kojiro Yoda