Title:
配線基板の製造方法
Document Type and Number:
Japanese Patent JP6991718
Kind Code:
B2
Abstract:
A method of making a wiring board includes forming a first capacitor carrier layer with a first embedded chip capacitor, a first insulation layer disposed on an upper surface, a second insulation layer disposed on a lower surface, first upper and lower conductive vias in conductive contact with a first electrode, and second upper and lower conductive vias in conductive contact with a second electrode. The method also includes forming a second capacitor carrier layer similar to the first. The method further includes forming a bonded laminate comprising in sequence an upper insulation layer, the first capacitor carrier layer, a center insulation layer, the second capacitor carrier layer, and a lower insulation layer. The method also includes forming a through-hole through the laminate and forming a conductive coating within the through-hole to provide a conductive through-hole. A wiring board also includes the bonded laminate and the embedded capacitors.
Inventors:
Keiichi Hirabayashi
Atsushi Sato
Youichi Miyazawa
Edmund Black Share
Brian W. Quinlan
Atsushi Sato
Youichi Miyazawa
Edmund Black Share
Brian W. Quinlan
Application Number:
JP2017015230A
Publication Date:
January 12, 2022
Filing Date:
January 31, 2017
Export Citation:
Assignee:
Shinko Electric Industry Co., Ltd.
International Classes:
H05K3/46
Domestic Patent References:
| JP2009194381A | ||||
| JP2009289805A | ||||
| JP2015225912A | ||||
| JP2013042164A |
Attorney, Agent or Firm:
Tadashige Ito
Tadahiko Ito
Tadahiko Ito
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