Title:
半導体集積回路の配線レイアウト方法
Document Type and Number:
Japanese Patent JP5218466
Kind Code:
B2
Inventors:
Rei Oshima
Yokota Noboru
Takashi Iida
Masafumi Takase
Shigenori Ichinose
Yokota Noboru
Takashi Iida
Masafumi Takase
Shigenori Ichinose
Application Number:
JP2010091094A
Publication Date:
June 26, 2013
Filing Date:
April 12, 2010
Export Citation:
Assignee:
Fujitsu Semiconductor Limited
International Classes:
H01L21/82; H01L21/3205; H01L21/768; H01L21/822; H01L23/522; H01L27/04
Domestic Patent References:
JP1066950A | ||||
JP3014265A | ||||
JP63199444A | ||||
JP7202145A | ||||
JP2025054A | ||||
JP61199647A | ||||
JP61244046A |
Attorney, Agent or Firm:
Tetsuo Hirado