Title:
WIRING FOR SEMICONDUCTOR INTEGRATED CIRCUIT AND ITS FORMATION
Document Type and Number:
Japanese Patent JPH01124238
Kind Code:
A
Abstract:
PURPOSE:To form a wiring composed of a Cu-SiO2 layer with the small number of processes by a method wherein a Cu layer to which a small amount of Si has been added is formed in advance and this layer is heat-treated in an atmosphere containing a very small amount of oxygen. CONSTITUTION:While a Cu target to which, e.g., 1-2wt.% Si has been added is sputtered, a Cu layer 3 with a thickness of about 0.7mum containing Si is formed on a silicon substrate 1 where an SiO2 insulating layer 2 has been formed in advance. An SiO2 layer with a thickness of about 0.5mum is formed on this Cu layer 3; this SiO2 layer is patterned by using a well-known lithographic technique; an SiO2 mask layer 4 which is used to etch the Cu layer is formed. Then, the Cu layer 3 which has been exposed from the SiO2 mask layer 4 is etched. After that, the SiO2 mask layer 4 is removed selectively, a Cu-layer wiring part 31 which has been processed to have a prescribed wiring pattern and whose width is about 1-2mum is obtained. After that, the silicon substrate 1 is heated at about 450 deg.C for about 30 minutes in an argon atmosphere which contains about 3% hydrogen and a very small amount of oxygen. As a result, the Cu-layer wiring part 31 is transformed into a Cu-SiO2 layer wiring part 32.
Inventors:
HOSHINO KAZUHIRO
BOKU YOSHIHIRO
BOKU YOSHIHIRO
Application Number:
JP28250187A
Publication Date:
May 17, 1989
Filing Date:
November 09, 1987
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
H01L21/3205; H01L21/28; H01L23/52; H01L29/43; (IPC1-7): H01L21/88; H01L29/46
Attorney, Agent or Firm:
Sadaichi Igita