Title:
半導体装置の配線構造体及びその形成方法
Document Type and Number:
Japanese Patent JP5037794
Kind Code:
B2
Abstract:
An interconnection structure for a semiconductor device includes an inter-level insulation layer disposed on a semiconductor substrate. First contact constructions penetrate the inter-level insulation layer. Second contact constructions penetrate the inter-level insulation layer. Metal interconnections connect the first contact constructions to the second contact constructions on the inter-level insulation layer. The first contact constructions include first and second plugs stacked in sequence and the second contact constructions include the second plug.
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Inventors:
Park Jin-sawa
Park Park
Xu-star
Gold and tin
Park Park
Xu-star
Gold and tin
Application Number:
JP2005071421A
Publication Date:
October 03, 2012
Filing Date:
March 14, 2005
Export Citation:
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
H01L21/3205; H01L21/768; H01L21/336; H01L21/4763; H01L21/8234; H01L21/8247; H01L27/088; H01L27/10; H01L27/115; H01L29/788; H01L29/792
Domestic Patent References:
| JP2002353334A | ||||
| JP2001102551A | ||||
| JP2000156480A |
Attorney, Agent or Firm:
Mikio Hatta
Yasuo Nara
Etsuko Saito
Katsuyuki Utani
Yasuo Nara
Etsuko Saito
Katsuyuki Utani