PURPOSE: To effectively utilize an I/O write cycle time and to prevent system performance from being reduced by latching an address from a CPU and an I/O write command and supplying the latched contents to an I/O device.

CONSTITUTION: Data from a data bus 4 connected to the CPU are latched by a latch circuit 3 and inputted to the I/O device 1. Similarly the data of an address bus 5 are latched by a latch circuit 11, decoded by a decoding circuit 8 and inputted to the I/O device 1. An I/O write command signal 6 is inputted to a latch circuit 13 and a latch timing control circuit 14 and a latch timing control signal 10 is used as a control signal for the latch circuits 3, 11, 13. When the writing time of the I/O device 1 is long and a queue time is required for the I/O write cycle of the CPU, the address data from the CPU and the I/O write command are latched and supplied to the I/O device 1.