Title:
演算処理装置およびその方法
Document Type and Number:
Japanese Patent JP4042215
Kind Code:
B2
Abstract:
A processing apparatus capable of reducing the size of the circuit, where in order to perform an operation "(A-B)xC", provision is made of multiplexers 500 to 5015 provided corresponding to each of all combinations of natural numbers i and j which receive as their inputs bit data Ai, Bi, and Cj, output the bit data Ai when the Cj has the logical value "1", and output the bit data Biwhen the Cj has the logical value "0", and the bit data output from the multiplexers 500 to 5015, data obtained by shifting the complement data of 2 of the data B by exactly n bits toward the most significant bit, the data B and the carry data as the carrying from the lower significant bit are added for every bit so as to add the bit data output from the multiplexers 500 to 5015 to the (i+j)th bit.
Inventors:
Koichi Onuma
Application Number:
JP16741898A
Publication Date:
February 06, 2008
Filing Date:
June 15, 1998
Export Citation:
Assignee:
ソニー株式会社
International Classes:
G06F7/53; G06F7/535; G06F7/523; G06F7/544; G06F7/62; G06F7/52
Domestic Patent References:
| JP58086637A | ||||
| JP57159346A | ||||
| JP63071729A |
Attorney, Agent or Firm:
Takahisa Sato