Title:
The command indicating the head and termination of a non-transaction code field which need the write back to permanent memory storage
Document Type and Number:
Japanese Patent JP6121010
Kind Code:
B2
Abstract:
A processor in described having an interface to non-volatile random access memory and logic circuitry. The logic circuitry is to identify cache lines modified by a transaction which views the non-volatile random access memory as the transaction's persistence storage. The logic circuitry is also to identify cache lines modified by a software process other than a transaction that also views said non-volatile random access memory as persistence storage.
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Inventors:
Wilhalm, Thomas
Application Number:
JP2016025122A
Publication Date:
April 26, 2017
Filing Date:
February 12, 2016
Export Citation:
Assignee:
INTEL CORPORATION
International Classes:
G06F12/08; G06F9/46; G06F12/0804
Domestic Patent References:
| JP2009537053A | ||||
| JP11096062A |
Foreign References:
| WO2008005687A2 | ||||
| US20110208921 | ||||
| US20100332807 | ||||
| US20130013899 | ||||
| WO2009122694A1 | ||||
| US20110004731 |
Attorney, Agent or Firm:
Longhua International Patent Service Corporation