Title:
The control method of an arithmetic processing unit and an arithmetic processing unit
Document Type and Number:
Japanese Patent JP6011194
Kind Code:
B2
Abstract:
A processor includes a cache write queue configured to store write requests, based on store instructions directed to a cache memory issued by an instruction issuing unit, into entries provided with stream_wait flag, and to output a write request including no stream_wait flag set thereon, from among the stored write requests, to a pipeline operating unit which performs pipeline operation with respect to the cache memory, the cache write queue being further configured to determine, when a stream flag attached to the store instruction is set, that there will be succeeding store instruction directed to a data area same as that accessed by the store instruction, to set the stream_wait flag so as to store the write request into the entry, to merge the write requests based on the store instructions, directed to the same data area, into a single write request, and then to hold the merged write request.
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Inventors:
Hideki Okawara
Application Number:
JP2012208692A
Publication Date:
October 19, 2016
Filing Date:
September 21, 2012
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F12/0804; G06F12/08
Domestic Patent References:
| JP10124391A | ||||
| JP2009134391A | ||||
| JP2006048163A | ||||
| JP2010134628A | ||||
| JP2009157886A |
Foreign References:
| US20090006605 |
Attorney, Agent or Firm:
Takayoshi Kokubun