Title:
The control method and memory control system of a memory controller and volatile memory
Document Type and Number:
Japanese Patent JP5917307
Kind Code:
B2
Abstract:
The memory controller is provided with a refresh clock generation unit, a control signal generation unit, and a refresh request generation unit. The refresh clock generation unit generates a clock obtained by frequency dividing a system clock, as a refresh clock. The control signal generation unit issues a refresh command to a memory, based on the refresh clock. The refresh request generation unit curtails, based on a specified refresh count in a specified refresh period determined by the memory, a supply to the control signal generation unit of a redundant refresh clock generated exceeding the specified refresh count, the refresh clock being generated within the specified refresh period.
Inventors:
Takayuki Matsumoto
Application Number:
JP2012132232A
Publication Date:
May 11, 2016
Filing Date:
June 11, 2012
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
G11C11/406
Domestic Patent References:
| JP6180986A | ||||
| JP10063563A |
Attorney, Agent or Firm:
Kato Asamichi
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