Title:
デジタル信号の遷移レートを低減する装置
Document Type and Number:
Japanese Patent JP4203544
Kind Code:
B2
Abstract:
A transition splitting apparatus and method reduce a maximum transition rate of a digital signal. The apparatus and method are particularly useful for digital signal processing in communications and for performing digital transition timing testing on a device under test. The apparatus and method split a digital signal into two or more signals, while preserving the relative timing of transitions in the digital signal. A high frequency signal is partitioned by the apparatus and method into a plurality of equivalent lower frequency signals without loss of transition timing information. The apparatus is implemented with readily available components. The maximum transition rate of a digital signal is reduced by a factor of two or more, and is proportional to the number of output signals. A plurality of the apparatuses may be cascaded together into a system to achieve even greater reductions in maximum transition rates.
More Like This:
| JPH0773288 | [Title of Invention] Digital Modulation Circuit |
| JPS6173413 | DIGITAL SIGNAL PROCESSING SYSTEM |
| JPS6086906 | VARIABLE DELAY CIRCUIT |
Inventors:
Johann Revoir
Ajay Koche
Ajay Koche
Application Number:
JP2002102233A
Publication Date:
January 07, 2009
Filing Date:
April 04, 2002
Export Citation:
Assignee:
Verigy(Singapore)Pte.Ltd.
International Classes:
H03H17/00; H03M5/06; H03M9/00; H04L7/00
Domestic Patent References:
| JP2000209075A | ||||
| JP2000183729A | ||||
| JP10268965A | ||||
| JP3041813A |
Attorney, Agent or Firm:
Patent business corporation Okada Fusimi Hirano