Title:
Laminated semiconductor die assemblies with improved thermal performance and related systems and methods
Document Type and Number:
Japanese Patent JP6339222
Kind Code:
B2
Abstract:
Stacked semiconductor die assemblies with improved thermal performance and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a stack of semiconductor dies and a thermally conductive casing at least partially enclosing the stack of semiconductor dies within an enclosure. A package substrate carries the thermally conductive casing, and an interposer is disposed between the thermally conductive casing and the stack of semiconductor dies. A peripheral portion of the interposer extends laterally beyond the stack of semiconductor dies and is coupled to a plurality of conductive members interposed between the peripheral portion and the package substrate.
Inventors:
Coupmans, michel
Luo, Syrian
Henbury, David Earl.
Luo, Syrian
Henbury, David Earl.
Application Number:
JP2016559399A
Publication Date:
June 06, 2018
Filing Date:
March 30, 2015
Export Citation:
Assignee:
APPLIED MATERIALS,INCORPORATED
International Classes:
H01L25/065; H01L25/07; H01L25/18
Domestic Patent References:
| JP2013538012A | ||||
| JP2012109572A | ||||
| JP2007234881A | ||||
| JP2000223645A | ||||
| JP2000156461A | ||||
| JP2004087700A |
Foreign References:
| WO2013074484A1 | ||||
| US6580611 | ||||
| US20100283085 | ||||
| WO2013074454A1 | ||||
| US20110140260 |
Attorney, Agent or Firm:
Yoshiyuki Osuga
Nomura Yasuhisa
Nomura Yasuhisa