Title:
A manufacturing method of a SOI wafer
Document Type and Number:
Japanese Patent JP5978764
Kind Code:
B2
Abstract:
The present invention provides a method for manufacturing an SOI wafer, in which an insulator film is formed at least on all surfaces of a base wafer, and while protecting a first part of the insulator film on a back surface on the opposite side from a bonded surface of the base wafer, a bonded wafer before separating a bond wafer along a layer of the implanted ion is brought into contact with a liquid capable of dissolving the insulator film or exposed to a gas capable of dissolving the insulator film, such that a second part of the insulator film interposed between the bond wafer and the base wafer is etched from an outer circumferential edge of the bonded wafer and toward the center of the bonded wafer. The method can control the terrace width, prevent the occurrence of an SOI island, and inhibit warping of the SOI wafer in a bonding process with a base wafer having an insulator film formed thereon.
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Inventors:
Koji Aga
Toru Ishitsuka
Toru Ishitsuka
Application Number:
JP2012119066A
Publication Date:
August 24, 2016
Filing Date:
May 24, 2012
Export Citation:
Assignee:
Shin-Etsu Semiconductor Co., Ltd.
International Classes:
H01L21/02; H01L21/265; H01L27/12
Domestic Patent References:
| JP11016861A | ||||
| JP8107091A | ||||
| JP2010199353A | ||||
| JP2008526038A | ||||
| JP2004022838A | ||||
| JP2011071193A |
Attorney, Agent or Firm:
Mikio Yoshimiya
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