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Patent Searching and Data


Title:
A manufacturing method of a chip resistor machine
Document Type and Number:
Japanese Patent JP6144136
Kind Code:
B2
Abstract:
The invention is to provide a chip-resistor manufacturing method in which chipping can be restrained from occurring in an intersection portion between each primary segmentation groove and each secondary segmentation groove. Primary segmentation grooves 21 each having an uneven depth are formed in one surface of a large substrate 20. Pairs of surface electrodes 3 extending across the primary segmentation grooves 21, resistive elements 5 each striding between the surface electrodes 3 paired with each other, etc. are formed in the one surface of the large substrate 20. Then, primary segmentation is performed on the large substrate 20 along the primary segmentation grooves 21 so as to open the surface side where the surface electrodes 3, the resistive elements 5, etc. are formed. Thus, a plurality of strip-like substrates 30 are obtained from the large substrate 20. During the primary segmentation, each primary segmentation groove 21 begins to break from electrode formation regions which are small in groove depth but strong, and then breaks in intersection portions which are large in groove depth but brittle. Accordingly, it is possible to perform primary segmentation on the primary segmentation groove 21 without applying a large load to the intersection portions which are low in strength. Thus, it is possible to prevent chipping from occurring in the intersection portions.

Inventors:
Kentaro Matsumoto
Uekane Fujitaro
Yuya Takegami
Application Number:
JP2013148791A
Publication Date:
June 07, 2017
Filing Date:
July 17, 2013
Export Citation:
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Assignee:
koa corporation
International Classes:
H01C17/00
Domestic Patent References:
JP2003086408A
JP2007165517A
JP6077001A
JP6087085A
JP4241401A
JP2005317927A
JP2003273272A
JP62151749U
JP2009302509A
JP2264405A
Attorney, Agent or Firm:
Patent Business Corporation Takewa International Patent Office