Title:
A manufacturing method of monolithic accumulation semiconductor structure and the above-mentioned semiconductor structure
Document Type and Number:
Japanese Patent JP6057096
Kind Code:
B2
Abstract:
A monolithic integrated semiconductor structure includes: A) an Si carrier layer, B) a layer having the composition BxAlyGazNtPv, wherein x=0-0.1, y=0-1, z=0-1, t=0-0.1 and v=0.9-1, C) a relaxation layer having the composition BxAlyGazInuPvSbw, wherein x=0-0.1, y=0-1, z=0-1, u=0-1, v=0-1 and w=0-1, wherein w and/or u is on the side facing toward layer A) or B) smaller than, equal to, or bigger than on the side facing away from layer A) or B) and wherein v=1−w and/or y=1−u−x−z, and D) a group III/V, semiconductor material. The sum of the above stoichiometric indices for all group III elements and for all group V elements are each equal to one.
Inventors:
Kunart, Bernadette
Application Number:
JP2014519416A
Publication Date:
January 11, 2017
Filing Date:
April 25, 2012
Export Citation:
Assignee:
N Espa Three/V Game Behr
International Classes:
H01L21/20; C23C16/30; C23C16/455; H01L21/205
Domestic Patent References:
| JP2008529260A | ||||
| JP10032165A | ||||
| JP1100976A | ||||
| JP2239614A | ||||
| JP2006041516A | ||||
| JP2003046120A | ||||
| JP1105527A |
Foreign References:
| US20080073639 |
Attorney, Agent or Firm:
▲吉▼川 俊雄
Kana Ichikawa
Kana Ichikawa
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