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Title:
MULTILAYER PRINTED WIRING BOARD, MANUFACTURING METHOD OF MULTILAYER PRINTED WIRING BOARD
Document Type and Number:
Japanese Patent JP2018060914
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a multilayer printed wiring board capable of suppressing positional deviation of the conductor pattern of a conductor layer of a core board from original position.SOLUTION: A multilayer printed wiring board includes a core board 2, a first build-up layer 31, and a second build-up layer 32. The first build-up layer 31 is formed by laminating a first isolating layer 61 and a first conductor layer 71 alternately. The second build-up layer 32 is formed by laminating a second isolating layer 62 and a second conductor layer 72 alternately. The core board 2, the first isolating layer 61 and the second isolating layer 62 have glass clothes 5, 8, 9. The glass clothes 5, 8, 9 are formed of warp threads 51, 81, 91 and weft threads 52, 82, 92, where the warp threads are narrower than the weft threads 52, 82, 92. Orientation of the warp threads 51, 81, 91 of the glass clothes 8, 9 of the first and second isolating layers 61, 62 adjoining the core board 2 is orthogonal to the orientation of the warp thread 51 of the glass cloth 5 of the core board 2.SELECTED DRAWING: Figure 1

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Inventors:
TOSHIMITSU KENICHI
ARAI DAISUKE
ISAJI KOICHI
FUJISAWA HIROYUKI
NAKAMURA YOSHIHIKO
Application Number:
JP2016197417A
Publication Date:
April 12, 2018
Filing Date:
October 05, 2016
Export Citation:
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Assignee:
PANASONIC IP MAN CORP
International Classes:
H05K3/46; H05K1/03
Domestic Patent References:
JP2006324642A2006-11-30
JP2002192521A2002-07-10
JP2005236216A2005-09-02
JPS5110362A1976-01-27
Foreign References:
WO2010140214A12010-12-09
Attorney, Agent or Firm:
Patent business corporation Hokuto patent office
Keisei Nishikawa
Mizuhiji Katsuhisa
Yoshishige Takeo