Title:
A manufacturing method of a semiconductor device and a semiconductor device
Document Type and Number:
Japanese Patent JP5919232
Kind Code:
B2
Abstract:
An objet of the present invention is to provide a semiconductor device with a new structure. Disclosed is a semiconductor device including a first transistor which includes a channel formation region on a substrate containing a semiconductor material, impurity regions formed with the channel formation region interposed therebetween, a first gate insulating layer over the channel formation region, a first gate electrode over the first gate insulating layer, and a first source electrode and a first drain electrode which are electrically connected to the impurity region; and a second transistor which includes a second gate electrode over the substrate containing a semiconductor material, a second gate insulating layer over the second gate electrode, an oxide semiconductor layer over the second gate insulating layer, and a second source electrode and a second drain electrode which are electrically connected to the oxide semiconductor layer.
Inventors:
Shunpei Yamazaki
Jun Koyama
Imai Kataro
Jun Koyama
Imai Kataro
Application Number:
JP2013157544A
Publication Date:
May 18, 2016
Filing Date:
July 30, 2013
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
H01L21/8234; H01L21/336; H01L21/8238; H01L21/8247; H01L27/08; H01L27/088; H01L27/092; H01L27/105; H01L27/115; H01L29/786; H01L29/788; H01L29/792
Domestic Patent References:
| JP5110392A | ||||
| JP2002368226A | ||||
| JP2009212443A | ||||
| JP2007103918A | ||||
| JP2009135350A | ||||
| JP11233789A | ||||
| JP2003101407A |
Foreign References:
| US20010015450 | ||||
| US20080023703 |
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