Title:
A manufacturing method of a semiconductor device and a semiconductor device
Document Type and Number:
Japanese Patent JP6050662
Kind Code:
B2
Abstract:
Provided is a miniaturized transistor with stable and high electrical characteristics with high yield. In a semiconductor device including the transistor in which an oxide semiconductor film, a gate insulating film, and a gate electrode layer are stacked in this order, a first sidewall insulating layer is provided in contact with a side surface of the gate electrode layer, and a second sidewall insulating layer is provided to cover a side surface of the first sidewall insulating layer. The first sidewall insulating layer is an aluminum oxide film in which a crevice with an even shape is formed on its side surface. The second sidewall insulating layer is provided to cover the crevice. A source electrode layer and a drain electrode layer are provided in contact with the oxide semiconductor film and the second sidewall insulating layer.
Inventors:
Kurata
Shinya Sasakawa
Muraoka Taiga
Tetsuhiro Tanaka
Junichi Koizuka
Shinya Sasakawa
Muraoka Taiga
Tetsuhiro Tanaka
Junichi Koizuka
Application Number:
JP2012256319A
Publication Date:
December 21, 2016
Filing Date:
November 22, 2012
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
H01L21/336; H01L21/8242; H01L21/8244; H01L21/8247; H01L27/10; H01L27/105; H01L27/108; H01L27/11; H01L27/115; H01L29/786; H01L29/788; H01L29/792
Domestic Patent References:
| JP2011109079A | ||||
| JP2008544522A | ||||
| JP2011124557A | ||||
| JP11168218A | ||||
| JP2007305819A |