Title:
A manufacturing method of a semiconductor device
Document Type and Number:
Japanese Patent JP6220948
Kind Code:
B2
Abstract:
The number of manufacturing steps is reduced to provide a semiconductor device with high productivity and low cost. A semiconductor device with low power consumption and high reliability is provided. A photolithography process for forming an island-shaped semiconductor layer is omitted, and a semiconductor device is manufactured through at least four photolithography processes: a step for forming a gate electrode (including a wiring or the like formed from the same layer), a step for forming a source electrode and a drain electrode (including a wiring or the like formed from the same layer), a step for forming a contact hole, and a step for forming a pixel electrode. In the step for forming the contact hole, a groove portion is formed, whereby formation of a parasitic transistor is prevented. The groove portion overlaps with the wiring with an insulating layer provided therebetween.
Inventors:
Jun Koyama
Application Number:
JP2016208683A
Publication Date:
October 25, 2017
Filing Date:
October 25, 2016
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
H01L29/786; G02F1/1368; G09F9/00; G09F9/30; H01L21/336; H01L51/50; H05B44/00
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