Title:
チャネル等化を実施するための方法及び装置
Document Type and Number:
Japanese Patent JP4700054
Kind Code:
B2
Abstract:
Methods, apparatuses, and systems are presented for performing channel equalization involving receiving a signal from a channel associated with inter-s interference (ISI), providing the received signal to an inductor, capacitor, resistance (LCR) network comprising a plurality of inductors and a plurality of capacitors, generating in the LCR network a first plurality of intermediate signals representing voltages associated with capacitors in the LCR network and a second plurality of intermediate signals representing currents associated with inductors in the LCR network, wherein the first plurality and second plurality of intermediate signals correspond to application of linearly independent impulse responses to the received signal, applying a corresponding one of a plurality of multiplier factors to each of the first plurality and second plurality of intermediate signals, and generating from the LCR network a resulting signal corresponding to an equalized version of the received signal.
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Inventors:
Pavan, shanti
Application Number:
JP2007516596A
Publication Date:
June 15, 2011
Filing Date:
June 09, 2005
Export Citation:
Assignee:
VITESSE SEMICONDUCTOR CORPORATION
International Classes:
H03F3/45; H03H21/00; H03F3/68; H03H7/01; H03H7/06; H03H7/075; H03H7/09; H03H11/04; H03H15/00; H04B3/06; H04L25/03; H04L25/08
Domestic Patent References:
| JP4233313A | ||||
| JP2228115A | ||||
| JP62160827A |
Attorney, Agent or Firm:
Atsushi Aoki
Jun Tsuruta
Tetsuro Shimada
Kurachi Yasuyuki
Shimichi Akihisa
Jun Tsuruta
Tetsuro Shimada
Kurachi Yasuyuki
Shimichi Akihisa