Title:
A method and a device which calibrate the write-in timing of a memory system
Document Type and Number:
Japanese Patent JP6199424
Kind Code:
B2
Abstract:
A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period. In a variation of this system, the phase detector on the memory chip is configured to receive signals including a clock signal, a marking signal and a data-strobe signal from the memory controller, wherein the marking signal includes a pulse which marks a specific clock cycle in the clock signal. In this variation, the phase detector is configured to use the marking signal to window the specific clock cycle in the clock signal, and to use the data-strobe signal to capture the windowed clock signal, thereby creating a feedback signal which is returned to the memory controller to facilitate calibration of the timing relationship.
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Inventors:
Giovanni Ni, Thomas
Gupta, Aroku
Ian Shaffer
Woo, Stephen, Sea.
Gupta, Aroku
Ian Shaffer
Woo, Stephen, Sea.
Application Number:
JP2016038721A
Publication Date:
September 20, 2017
Filing Date:
March 01, 2016
Export Citation:
Assignee:
Rambus Incorporated
International Classes:
G06F12/00; G11C11/407; G11C11/4076
Foreign References:
| US20060262613 | ||||
| US20050010834 |
Other References:
Raj Mahajan,Memory Design Considerations When Migrating to DDR3 Interfaces from DDR2,MemCore White Paper,MemCore Inc.,2007年 3月 5日,p.1-9,[online],インターネット,URL,http://web.archive.org/web/20070929161408/http://www.memcoreinc.com/DDR3WP061207.pdf
Attorney, Agent or Firm:
Yoshiyuki Inaba
Toshifumi Onuki
Mutsumi Sato
Toshifumi Onuki
Mutsumi Sato