Title:
半導体装置に対する同時動作信号ノイズに基づいてジッタを見積る方法、その見積りに使用する同時動作信号ノイズ量対ジッタ量相関関係を算出する方法、それらを実現するプログラム、及び半導体装置及びそれが搭載されたプリント回路基板の設計方法
Document Type and Number:
Japanese Patent JP5228481
Kind Code:
B2
Abstract:
An SSO noise calculating unit estimates the amount of simultaneously operating signal noise caused by simultaneous operations of input/output pins peripheral to a power supply voltage pin as a center. A PLL jitter calculating unit estimates the amount of jitter occurring at the power supply voltage pin by using as an input the estimated amount of simultaneously operating signal noise, and by referencing a correlation between the amount of simultaneously operating signal noise and the amount of jitter, which indicates a correlation calculated beforehand between the amount of simultaneously operating signal noise and the amount of jitter.
Inventors:
Yasuo Kasaki
Application Number:
JP2007341436A
Publication Date:
July 03, 2013
Filing Date:
December 28, 2007
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F17/50; H01L21/82
Domestic Patent References:
| JP7073219A | ||||
| JP2006031510A | ||||
| JP2005038400A | ||||
| JP2009140265A | ||||
| JP2008059553A |
Attorney, Agent or Firm:
Yoshiyuki Osuga
virtue Tamio Ei
virtue Tamio Ei